1. Field of the Invention
The present invention relates to a host I.sup.2 C controller for accelerated reading of I.sup.2 C EEPROMs.
2. Description of the Related Art
Use of I.sup.2 C (Inter-Integrated Circuit) devices in personal computer systems has become prevalent. Today's I.sup.2 C bus is typically used to communicate with a Serial Presence Detect (SPD) device on memory modules (DIMMs), Extended System Configuration Data (ESCD) storage devices, temperature sensors, and even batteries. An SPD device may hold data on the speed, size, or type of the related module. The device typically used as an SPD device or an ESCD storage device is an I.sup.2 C EEPROM.
A read access to a random address of an I.sup.2 C EEPROM is referred to as a Random Read command. A Random Read command is issued by a master such as firmware running on a controller, code residing in an embedded controller, an application, or the operating system itself. According to I.sup.2 C EEPROM protocol, a Random Read command requires a "dummy" byte write sequence to load a data word address into the EEPROM. The data word address informs the EEPROM of the memory location that a master is seeking to access. The "dummy" byte write also allows the master to send a control byte to the I.sup.2 C EEPROM. The control byte typically includes a four bit slave type, three device select bits, and a read/write bit which is set to a write operation. Because most accesses to EEPROMs are reads from a random address, and the "dummy" byte sequence may be comprised of two or three bytes depending on the size of the EEPROM's address space, the "dummy" byte write sequence is communication overhead that has slowed data accesses to I.sup.2 C EEPROMs.
I.sup.2 C EEPROMs also support a Current Address Read command. A Current Address Read command is a read access to the next sequential address of the EEPROM. After each read or write operation, the address counter of an EEPROM maintains the last accessed address, incremented by a byte or word. Because the address counter already holds the address to be accessed, a Current Address Read command is executed without the overhead of the "dummy" byte write sequence. Since a Random Read command requires a "dummy" byte write sequence, a Random Read command has twice the access time of a Current Address Read command. Thus, the approach has been to reduce communication overhead by minimizing the issuance of Random Read commands.
To determine when a Current Address Read command may be issued instead of a Random Address Read command, software has been used to determine when requested data is at an address contiguous to a previously accessed EEPROM address. When a read request is to the next sequential EEPROM location, the software issues a Current Address Read command instead of a Random Read command. Because, for example, multiple portions of a system's BIOS attempt to access I.sup.2 C EEPROMs through a host I.sup.2 C controller, complex software has undesirably been necessary to keep track of the last EEPROM address accessed while taking account of intervening reads by those different portions of code.
Also, in order to support both a Current Address Read command and a Random Read command, two command sets had to be defined as bus command protocols. Such bus command protocols have been used with buses compatible with I.sup.2 C protocol. For example, Intel has defined for its System Management Bus a first command protocol, Receive Byte, corresponding to a Current Address Read command, and a separate command protocol, Read Byte, corresponding to a Random Read command. Intel's System Management Bus has I.sup.2 C as a backbone. Thus, the capability of selecting either a Random Read command or a Current Address Read command when appropriate has undesirably required code that supports two different command protocols. Further, I.sup.2 C controllers, which serve as an interface between a microprocessor and an I.sup.2 C bus, have not, so far as is known, played a role in tracking EEPROM read accesses.